The SP of S3B512C single-chip CMOS micro-controller is designed and packaged specifically for "Biometric Smart Card" applications.

The Cortex-M33 CPU architecture of the SP of S3B512C microcontroller
follows the Harvard style, that is, it has separate program memory and data memory. Both instruction and data can be fetched simultaneously without causing a stall, using separate paths for memory access.

The main security features of the SP of S3B512C integrated circuit are:

• Secure fingerprint image capture and feature extraction provided by TOE SP firmware, integrity protected.
• Access control of Users to Flash memory positions where SP firmware is executed.
• TOE Unique Identification
• Countermeasures to avoid attackers reproduction of fingerprint data.
• An AES hardware block supporting AES encryption and decryption with 128-bit, 192-bit and 256-bit keys in ECB mode. The AES block supports encryption of fingerprint features to be sent to SE of S3B512C.

Note SE (Secure Element) is not TOE.